The present invention relates to the design of studs and connecting line joints in multilayer electrical circuits and particularly, to the extending of the connecting line beyond an asymmetric stud in the length direction of the line without significant overhang of the line in the width direction of the line for minimizing induced stresses in order to reduce voids and crack growth in the region where the connecting line is joined to the stud.
In the manufacture of multilevel integrated circuits used in computers and other electrical devices, reliability is a constant concern. Poor reliability adversely impacts yield and results in a high incidence of field failures and product returns. Although there are a number of causes for such failures including contamination, corrosion, misalignment and so forth, experience has shown that in many instances the failure is due to the fracture of studs which connect metal conducting lines between circuit containing conductor levels of multilayer circuit structures. The fracture of the studs is a result of stress resulting from thermal mismatch between the conducting layer and the passivation layer during temperature excursion and from thermally activated voiding processes.
Thus, the reduction of the thermal stress is one of the most important factors in improving reliability. It has been discovered that most stud failures occur at the studs located in the vicinity of the end of the metal conducting line. Finite-element calculation performed by the inventors shows that the stress in the studs at the end of the metal conducting lines are approximately 20 to 40 percent higher than the stress in the studs located in the middle of the line. Therefore, reduction of the stresses in the studs at the end of the metal conducting lines is of utmost importance.
Finite-element modeling results and SEM micrographs also show that the voids formed in the studs are primarily caused by tensile normal or hydrostatic stresses. Moreover, the location for voids to grow depends on the range of the temperature excursion and the duration at a particular temperature to which the circuit is exposed. In addition to reducing stud failures by optimizing the thermal cycling of the fabrication process, which optimization tends to be process limited, the present invention provides for reduced stud failure by optimizing the design of the stud and metal conducting line joint.